A 1-Msps 500-Node FORCE Learning Accelerator for Reservoir Computing

DOI Web Site 参考文献2件 オープンアクセス
  • Yoshida Kose
    Graduate School of Information Science and Technology, Hokkaido University
  • Akai-Kasaya Megumi
    Graduate School of Information Science and Technology, Hokkaido University
  • Asai Tetsuya
    Graduate School of Information Science and Technology, Hokkaido University

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説明

<p>A major issue in the conventional First-Order Reduced and Controlled Error (FORCE) learning architecture is the low processing speed due to extensive matrix-vector calculations for learning. In this study, we present the field programmable gate array architecture of FORCE learning that achieves the processing of 1-Msps 500-Node data. As a result, the learning was accomplished approximately 3,400 times faster while maintaining the original accuracy in a simulation under specified conditions.</p>

収録刊行物

  • 信号処理

    信号処理 26 (4), 103-106, 2022-07-01

    信号処理学会

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