A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations
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- Jin Xing
- School of Electronics and Information Technology, Sun Yat-sen University
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- Yin Ningyuan
- School of Microelectronics Science and Technology, Sun Yat-sen University
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- Chen Weichong
- School of Microelectronics Science and Technology, Sun Yat-sen University
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- Li Ximing
- School of Electronics and Information Technology, Sun Yat-sen University
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- Zhao Guihua
- School of Electronics and Information Technology, Sun Yat-sen University
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- Yu Zhiyi
- School of Microelectronics Science and Technology, Sun Yat-sen University Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems, Sun Yat-sen University
Abstract
<p>Traditional von Neumann architecture bottlenecks such as the “memory wall” limit artificial intelligence (AI) development, and in-memory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.</p>
Journal
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- IEICE Electronics Express
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IEICE Electronics Express 20 (11), 20230152-20230152, 2023-06-10
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1390014945747176704
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- ISSN
- 13492543
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
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- Abstract License Flag
- Disallowed