書誌事項
- タイトル別名
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- Impact of the Device Size and N-type Isolation Layer Voltage on the Negative Input Withstand Capability of Fully Isolated nLDMOS
抄録
<p>This paper presents the negative drain input measurements of fully isolated nLDMOS which is fabricated by a low-cost process without any additional epitaxial growth. The critical drain current which causes the parasitic PNP activation is proposed as the index of the negative drain input withstand capability. The device size dependence measurements show that the negative drain input withstand capability decreases as the internal LDMOS area increases which is surrounded by the n-type isolation layer electrode. And, the bias application measurements to n-type isolation layer show that the trade-off relation between the anomalous substrate leakage and the parasitic PNP activation; that is, the higher applied bias suppresses the parasitic PNP activation but makes the anomalous substrate leakage larger.</p>
収録刊行物
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- 電気学会論文誌C(電子・情報・システム部門誌)
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電気学会論文誌C(電子・情報・システム部門誌) 144 (3), 217-220, 2024-03-01
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390017843890883328
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- ISSN
- 13488155
- 03854221
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- Crossref
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- 抄録ライセンスフラグ
- 使用不可