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- XU Meng
- National ASIC Research Center, Southeast University, China
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- JI Xincun
- National ASIC Research Center, Southeast University, China
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- WU Jianhui
- National ASIC Research Center, Southeast University, China
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- ZHANG Meng
- National ASIC Research Center, Southeast University, China
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説明
This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13µm, 1.2V CMOS process. Experiments show that when the clock frequency is 32MHz, the power consumption of the proposed decoder is 38.4mW, the energy efficiency is 53.3pJ/bit/ite and the core area is 1.8mm2.
収録刊行物
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- IEICE Transactions on Communications
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IEICE Transactions on Communications E96.B (4), 939-947, 2013
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390282679352618240
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- NII論文ID
- 10031182798
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- NII書誌ID
- AA10826261
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- ISSN
- 17451345
- 09168516
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可