A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks

DOI Web Site 40 References
  • XU Meng
    National ASIC Research Center, Southeast University, China
  • JI Xincun
    National ASIC Research Center, Southeast University, China
  • WU Jianhui
    National ASIC Research Center, Southeast University, China
  • ZHANG Meng
    National ASIC Research Center, Southeast University, China

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This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13µm, 1.2V CMOS process. Experiments show that when the clock frequency is 32MHz, the power consumption of the proposed decoder is 38.4mW, the energy efficiency is 53.3pJ/bit/ite and the core area is 1.8mm2.

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