A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits

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  • YAMATO Yuta
    Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology The Institute of Electronics, Information and Communication Engineers
  • NAKAMURA Yusuke
    Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology
  • MIYASE Kohei
    Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology The Institute of Electronics, Information and Communication Engineers
  • WEN Xiaoqing
    Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology The Institute of Electronics, Information and Communication Engineers
  • KAJIHARA Seiji
    Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology The Institute of Electronics, Information and Communication Engineers

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Per-test diagnosis based on the X-fault model is an effective approach for a circuit with physical defects of non-deterministic logic behavior. However, the extensive use of vias and buffers in a deep-submicron circuit and the unpredictable order relation among threshold voltages at the fanout branches of a gate have not been fully addressed by conventional per-test X-fault diagnosis. To take these factors into consideration, this paper proposes an improved per-test X-fault diagnosis method, featuring (1) an extended X-fault model to handle vias and buffers and (2) the use of occurrence probabilities of logic behaviors for a physical defect to handle the unpredictable relation among threshold voltages. Experimental results show the effectiveness of the proposed method.

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