Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism
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- YE Jiongyao
- Graduate School of Information, Productions and Systems, Waseda University
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- HU Yingtao
- Graduate School of Information, Productions and Systems, Waseda University
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- DING Hongfeng
- Graduate School of Information, Productions and Systems, Waseda University
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- WATANABE Takahiro
- Graduate School of Information, Productions and Systems, Waseda University
書誌事項
- 公開日
- 2011
- 資源種別
- journal article
- DOI
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- 10.1587/transinf.e94.d.1398
- 公開者
- 一般社団法人 電子情報通信学会
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説明
Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the power-efficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.
収録刊行物
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E94-D (7), 1398-1408, 2011
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390282679354094080
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- NII論文ID
- 10029805481
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- NII書誌ID
- AA10826272
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- ISSN
- 17451361
- 09168532
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- 本文言語コード
- en
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- 資料種別
- journal article
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
- OpenAIRE
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- 抄録ライセンスフラグ
- 使用不可