On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
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- TOMITA Akihiro
- Kyushu Institute of Technology
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- WEN Xiaoqing
- Kyushu Institute of Technology
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- SATO Yasuo
- Kyushu Institute of Technology
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- KAJIHARA Seiji
- Kyushu Institute of Technology
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- MIYASE Kohei
- Kyushu Institute of Technology
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- HOLST Stefan
- Kyushu Institute of Technology
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- GIRARD Patrick
- LIRMM
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- TEHRANIPOOR Mohammad
- University of Connecticut
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- WANG Laung-Terng
- SynTest Technologies, Inc.
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Abstract
The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking,vector-masking) to block them from reaching the multiple-input signature register(MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.
Journal
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E97.D (10), 2706-2718, 2014
The Institute of Electronics, Information and Communication Engineers
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Details
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- CRID
- 1390282679355372672
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- NII Article ID
- 130004696754
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- NII Book ID
- AA10826272
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- ISSN
- 17451361
- 09168532
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- HANDLE
- 10228/00007527
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- Text Lang
- en
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- Data Source
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- JaLC
- IRDB
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed