Protection of On-chip Memory Systems against Multiple Cell Upsets Using Double-adjacent Error Correction Codes

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As semiconductor devices scale into deep sub-micron regime, the reliability issue due to radiation-induced soft errors increases in on-chip memory systems. Neutron-induced soft errors transiently upset adjacent information of multiple cells in these systems. Although single error correction and double error detection (SEC–DED) codes have been employed to protect on-chip memories from soft errors, they are not sufficient against multiple cell upsets (MCUs). SEC–DED and double adjacent error correction (SEC–DED–DAEC) codes have recently been proposed to address this problem. However, these codes do not the resolve mis-correction of double non-adjacent errors because syndromes for double non-adjacent errors are equal to that of double adjacent errors. The occurrence of this mis-correction in region of critical memory section such as operating systems may lead to system malfunction. To eliminate mis-correction, the syndrome spaces for double adjacent and double non-adjacent errors are not shared using the matrix with reversed colexicographic order. The proposed codes are implemented using hardware description language and synthesized using 32 nm technology library. The results show that there is no mis-correction in the proposed codes. In addition, the performance enhancement of the decoder is approximately 51.9% compared to double error correction codes for on-chip memories. The proposed SEC–DED–DAEC codes is suitable for protecting on-chip memory applications from MCUs-type soft errors.

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