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- Zhang Yu
- Graduate School of Information, Production and Systems, Waseda University
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- Liao Yun-Ting
- Graduate School of Information, Production and Systems, Waseda University
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- Chen Kui-Ting
- Research Center of Information, Production and Systems, Waseda University
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- Baba Takaaki
- Graduate School of Information, Production and Systems, Waseda University
説明
For many mathematical applications, the conventional coordinate rotation digital computer (CORDIC) algorithm can achieve high efficiency. However, the iterative procedure of the conventional CORDIC algorithm is inefficient owing to its rotation strategy. Chen et al. proposed a CORDIC algorithm with an improved rotation strategy to reduce the number of unnecessary iterations of the CORDIC algorithm. As a result, the calculation speed can be improved to four times than that of the conventional CORDIC hardware when the improved rotation strategy can finish its own functions within one clock cycle. However, the complexity of the improved rotation strategy is greatly increased, making it difficult to finish each rotation within one clock cycle. To overcome this difficulty, a hardware architecture for CORDIC with an improved rotation strategy is proposed to ensure that the improved rotation strategy can be finished within one clock cycle.
収録刊行物
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- 信号処理
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信号処理 20 (4), 141-144, 2016
信号処理学会
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詳細情報 詳細情報について
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- CRID
- 1390282679440652672
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- NII論文ID
- 130005165811
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- ISSN
- 18801013
- 13426230
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可