Analyses and Measurements of Propagation of Substrate Noise of CMOS Digital Circuit
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- Murasaka Yoshitaka
- Faculty of Engineering, Hiroshima University
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- Nagata Makoto
- Faculty of Engineering, Hiroshima University
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- Morie Takashi
- Faculty of Engineering, Hiroshima University
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- Iwata Atsushi
- Faculty of Engineering, Hiroshima University
Bibliographic Information
- Other Title
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- CMOSデジタル回路における基板雑音の伝搬特性解析と実測評価
- CMOS デジタル カイロ ニ オケル キバン ザツオン ノ デンパン トクセイ カイセキ ト ジッソク ヒョウカ
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Abstract
Analyses of the substrate noise propagation in the silicon substrate, which are injected during switching operations of logic circuits, are necessary for high performance mixed analog-digital LSI circuits. An equivalent circuit of the CMOS logic noise source, and an F-matrix equivalent circuit model of the substrate with metallic ground wiring systems, are used for simulating the noise generation and propagation in a substrate noise evaluation test chip. Simulated and measured results are very consistent in waveform shapes, in attenuation effects by the propagation, and also in the peak noise amplitudes approximately within 15%.
Journal
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- ITE Technical Report
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ITE Technical Report 24.52 (0), 9-14, 2000
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Details 詳細情報について
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- CRID
- 1390282679500590848
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- NII Article ID
- 110003688170
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- NII Book ID
- AN1059086X
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- ISSN
- 24241970
- 13426893
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- NDL BIB ID
- 5549180
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL
- CiNii Articles
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- Abstract License Flag
- Disallowed