High Performance Implementation of Decoding Variable Length Codes on Media Processor

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  • メディアプロセッサにおける可変長復号処理の高速化(マルチメディア通信とQoS, VoIP, ストリーミング, 一般)
  • メディアプロセッサにおける可変長復号処理の高速化
  • メディアプロセッサ ニ オケル カヘンチョウフクゴウ ショリ ノ コウソクカ

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Abstract

SIMD-type instructions and/or VLIW architecture are well-known features of high-performance processors. Although these features are effective for data-parallel algorithms, they have (almost) no effect for sequential algorithms such as decoding variable length codes. In order to address this issue, the media processor MAPCA has a co-processor for processing variable length code in addition to its 136-bit VLIW processor. Our prototype MPEG-4 decoder runs about 3.1 times faster than that using only the VLIW processor on MAPCA.

Journal

  • ITE Technical Report

    ITE Technical Report 26.48 (0), 19-24, 2002

    The Institute of Image Information and Television Engineers

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