Low Power Circuits for the Single-Slope Column-Parallel A/D Converter

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Other Title
  • シングルスロープ型列並列A/D変換方式の低消費電力化回路検討(固体撮像技術)
  • シングルスロープ型列並列A/D変換方式の低消費電力化回路検討
  • シングルスロープガタレツ ヘイレツ A D ヘンカン ホウシキ ノ テイショウヒ デンリョクカ カイロ ケントウ

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Abstract

A high data rate and a high resolution of a single-slope column-parallel A/D converter in the CMOS image sensor requires a fast system clock, and it causes large power consumption on the digital circuit region. This paper describes two low power circuits for the digital region of the single-slope column-parallel A/D converter. One is a latch circuit of a dynamic comparator for the gray-code counter data, and the other is a low power current sense amplifier using push-pull CMOS inverter. Simulation results show effectiveness for low power operation.

Journal

  • ITE Technical Report

    ITE Technical Report 34.16 (0), 47-50, 2010

    The Institute of Image Information and Television Engineers

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