Evaluation and Analysis of Substrate Noise in a Microprocessor
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- BANDO Yoji
- Department of Computer and Systems Engineering, Kobe University
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- KOSAKA Daisuke
- A-R-Tec corp.
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- YOKOMIZO Goichi
- STARC
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- TSUBOI Kunihiko
- STARC
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- SHIUN LI Ying
- Apache Design Solutions, Inc.
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- LIN Shen
- Apache Design Solutions, Inc.
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- NAGATA Makoto
- Department of Computer and Systems Engineering, Kobe University:A-R-Tec corp.
Bibliographic Information
- Other Title
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- マイクロプロセッサにおける基板ノイズの評価と解析(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
- マイクロプロセッサにおける基板ノイズの評価と解析
- マイクロプロセッサ ニ オケル キバン ノイズ ノ ヒョウカ ト カイセキ
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Abstract
An integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through comparison with on-chip noise measurements of a microprocessor chip in a 90-nm CMOS technology. The test chip includes 12 pairs of power and ground noise monitors within a processor and also embedds substrate noise evaluation areas with 120 probing points, realizing power and substrate noise measurements in terms of time-domain dynamic waveforms and spacial distribution. In addition to noise generation in digital circuits, noise propagation through on-chip silicon substrate and of chip package and board impedances needs to be carefully considered for quantitative and quality power noise simulation.
Journal
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- ITE Technical Report
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ITE Technical Report 33.39 (0), 11-14, 2009
The Institute of Image Information and Television Engineers
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Details 詳細情報について
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- CRID
- 1390282679504053888
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- NII Article ID
- 110007484183
- 10031113268
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- NII Book ID
- AN1059086X
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- ISSN
- 24241970
- 13426893
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- NDL BIB ID
- 10445537
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL
- CiNii Articles
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- Abstract License Flag
- Disallowed
