Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power

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  • 極低電力サブスレッショルド・ディジタル回路のオンチップ遅延バラツキ補正技術(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
  • 極低電力サブスレッショルド・ディジタル回路のオンチップ遅延バラツキ補正技術
  • キョクテイ デンリョク サブスレッショルド ディジタル カイロ ノ オンチップ チエン バラツキ ホセイ ギジュツ

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Abstract

Subthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication process have significant impact on the circuit performance. In subthreshold digital circuits, delay time changes exponentially with threshold-voltage variations. To solve this problem, we propose a delay-compensation technique for subthreshold digital circuits. On-chip threshold-voltage monitoring and supply-voltage scaling are adopted to mitigate threshold-voltage variations. As examples of subthreshold digital circuits, we have evaluated the delay time in a ring oscillator and an 8-bit ripple carry adder. With the proposed techinque, the delay time can be improved from log-normal to normal distribution.

Journal

  • ITE Technical Report

    ITE Technical Report 33.39 (0), 165-170, 2009

    The Institute of Image Information and Television Engineers

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