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A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor
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- Sato Gota
- Sony
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- Sukegawa Shunichi
- Sony
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- Umebayashi Taku
- Sony
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- Kawanobe Hiroshi
- Sony
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- Koseki Ken
- Sony LSI Design
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- Hirota Isao
- Sony
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- Haruta Tsutomu
- Sony
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- Kasai Masanori
- Sony
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- Fukumoto Koji
- Sony
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- Wakano Toshifumi
- Sony
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- Inoue Keishi
- Sony Semiconductor
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- Takahashi Hiroshi
- Sony
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- Nagano Takashi
- Sony
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- Nitta Yoshikazu
- Sony
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- Hirayama Teruo
- Sony
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- Nakajima Tsutomu
- Sony
Bibliographic Information
- Other Title
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- 1/4型800万画素積層型BI CMOSイメージセンサ(固体撮像技術および一般~IEDM, SPIE EI, ISSCC特集~)
- 1/4型800万画素積層型BI CMOSイメージセンサ
- 1/4ガタ 800マンカクソ セキソウガタ BI CMOS イメージセンサ
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Description
To realize a small chip size image sensor with the additional functions, we developed a stacked CMOS image sensor (CIS), which is composed of conventional back illuminated (BI) CMOS image sensor process technology and standard logic process technology. We have achieved 30% reduction in the chip size compared to the same optical size conventional BI-CIS regardless of addition function, also 24dB above the conventional dynamic range is obtained with a unique signal processing technology in high dynamic range (HDR) mode.
Journal
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- ITE Technical Report
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ITE Technical Report 37.19 (0), 31-34, 2013
The Institute of Image Information and Television Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1390282679506211328
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- NII Article ID
- 110009597634
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- NII Book ID
- AN1059086X
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- ISSN
- 24241970
- 13426893
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- NDL BIB ID
- 024388285
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL Search
- CiNii Articles
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- Abstract License Flag
- Disallowed