書誌事項
- タイトル別名
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- Vertical Double-Gate MOSFET Device Technology
- タテガタ ダブルゲート MOSFET デバイス ギジュツ
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抄録
The Silicon device technology is facing to several difficulties. Especially, explosion of power consumption due to short channel effects (SCEs) becomes the biggest issue in further device scaling down. Fortunately, double-gate (DG) MOSFETs have promising potential to overcome this obstacle. The DG-MOSFET is recognized to be the most scalable MOSFET for its high SCEs immunity. In addition, independent DG-MOSFET (4T-DG-MOSFET) has great advantage to enable the threshold voltage control for the flexible power management. Through this work, we have realized ideal DG-MOSFETs using newly-developed vertical DG-MOSFET device technology. This article presents the effectiveness of the vertical DG-MOSFETs in future high-performance and ultra-low-power CMOS circuits.
収録刊行物
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- 電気学会論文誌Ｃ（電子・情報・システム部門誌）
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電気学会論文誌Ｃ（電子・情報・システム部門誌） 126 (6), 702-707, 2006
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390282679580492160
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- NII論文ID
- 10017582622
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 7979234
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可