書誌事項
- タイトル別名
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- Design Technology of Stacked Type DTMOS
- セキソウ コウゾウ DTMOS(スタックガタ DTMOS)ノ ケントウ
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Stacked type DTMOS which enables to realize both high-speed low-power characteristics of FinFET type DTMOS and small pattern area of stacked transistor has been newly proposed. The delay time of substrate of stacked type DTMOS can be reduced to less than 10% compared with that of conventional FinFET type DTMOS by using the sidewall connection between gate and substrate. By using stacked structure of NMOS with (110) substrate on PMOS with (100) substrate high speed performance with the optimized mobility value can be realized without sacrificing the pattern area. Furthermore, the pattern area of inverter/NAND circuit, LSI for communication and DRAM buffer circuit with stacked type DTMOS has been compared with that of conventional FinFET type DTMOS. Newly proposed stacked type DTMOS is a promising candidate for realizing high performance system LSI such as the microprocessor of GHz operation.
収録刊行物
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- 電気学会論文誌Ｃ（電子・情報・システム部門誌）
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電気学会論文誌Ｃ（電子・情報・システム部門誌） 132 (12), 1927-1933, 2012
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390282679585206016
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- NII論文ID
- 10031129668
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 024253252
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
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- 抄録ライセンスフラグ
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