書誌事項
- タイトル別名
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- Architecture Aware Fault Analysis Based on Differential Presumption for Multiple Errors and its Evaluation
- アーキテクチャ オ コウリョ シタ フクスウ エラー ノ サブン スイテイ ニ モトズク フォールト カイセキ ト ソノ ヒョウカ
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抄録
Recently, the number of electronic devices handling confidential information has increased. In these devices, cryptographic circuits are applied to protect the confidential information. It has been sufficiently confirmed that the decryption of the encryption standards used in cryptographic circuits is computationally impossible. However, it was recently reported that when a theoretically safe encryption algorithm was embedded in the hardware, confidential information could be illegally specified by fault analysis attacks. Here, fault analysis attacks specify the secret keys by intentionally generating a fault during the encryption processing and by comparing the fault and normal cases. Almost all previous studies have strictly constraints related to the number of faults and the position of faults. Therefore, this study proposes a new fault analysis attack which has no constraint for the number of faults and considers the architecture. Experimental results using FPGA show the validity of the proposed attack.
収録刊行物
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- 電気学会論文誌C(電子・情報・システム部門誌)
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電気学会論文誌C(電子・情報・システム部門誌) 132 (12), 1888-1896, 2012
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390282679585224576
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- NII論文ID
- 10031129662
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 024253161
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可