Design Technology of Stacked Type Chain PRAM

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  • Kato Sho
    Department of Information Science, Shonan Institute of Technology
  • Watanabe Shigeyoshi
    Department of Information Science, Shonan Institute of Technology

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  • 積層方式Chain構造PRAMの設計法
  • セキソウ ホウシキ Chain コウゾウ PRAM ノ セッケイホウ

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Abstract

A stacked type chain PRAM which enables to realize lower cost than flash memory has been proposed. The newly proposed memory cell is consisted with a PCM for data storage and a MOS transistor connected in parallel. This memory cell is connected in series for realizing the chain structure. Cell structure, the design method for realizing stable read and write operation, and core circuit for the stacked type chain PRAM have been described. Newly proposed memory cell has been designed to adopt BiCS (Bit Cost Scalable) process technology for realizing low-cost memory. The design of the resistance of PCM and the pass transistor is key issue for realizing stable operation. For designing the row decoder, the circuit concept of the stacked FeRAM with the NAND structure cell has been successfully adopted with SGT. The newly proposed stacked type chain PRAM is a promising candidate for realizing high-speed and low-power future non-volatile semiconductor memory.

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