書誌事項
- タイトル別名
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- A Structure Learning Method for Block-Based Neural Networks
- ブロック コウゾウ ニューラルネットワーク ノ コウゾウ ガクシュウホウ
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In recent years a study of the evolvable hardware (EHW) which can adapt to new and unknown environments attracts much attention among hardware designers. EHW is reconfigurable hardware and can be implemented combining reconfigurable devices such as FPGA (Field Programmable Gate Array) and evolutionary computation such as Genetic Algorithms (GAs). As such research of EHW, Block-Based Neural Networks (BBNNs) have been proposed. BBNNs have simplified network structures and their weights and network structure can be optimized at the same time using GAs. The learning of BBNNs using GAs are, however, not efficient because genetic operators, such as crossover and mutation, often alter the network structure drastically. In this paper, we propose a new update method of the network structure in order to solve this problem. The proposed method is based on locally update of the network structure and is able to maintain the structural similarity. In addition, we introduce an evaluation method which determines the convergence of weight learning in order to improve the efficiency of learning. In the proposed method, the network structure is updated after the learning of weights converges. In order to evaluate the proposed method, we implement BBNNs on FPGA. As a result, the proposed method is able to learn the weights and structure simultaneously, and we confirmed it is effective compared with the conventional method.
収録刊行物
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- 電気学会論文誌Ｃ（電子・情報・システム部門誌）
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電気学会論文誌Ｃ（電子・情報・システム部門誌） 133 (10), 1976-1982, 2013
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390282679585886720
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- NII論文ID
- 10031200988
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 024946829
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可