Accurate Clock Period Comparison for PLL Using Phase-Shift Direction Detector
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- Makihara Yukinobu
- Graduate School of Information Science and Technology, Hokkaido University
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- Ikebe Masayuki
- Graduate School of Information Science and Technology, Hokkaido University
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- Motohisa Junichi
- Graduate School of Information Science and Technology, Hokkaido University
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- Sano Eiichi
- Research Center for Integrated Quantum Electronics, Hokkaido University
Bibliographic Information
- Other Title
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- 位相変動方向検出回路による周期比較方式PLLの高精度化
- イソウ ヘンドウ ホウコウ ケンシュツ カイロ ニ ヨル シュウキ ヒカク ホウシキ PLL ノ コウセイドカ
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Abstract
We proposed a new architecture for a phase-locked loop (PLL) obtained by comparing clock periods. We evaluated the use of a clock-period comparator (CPC) for the digitally controlled PLL we propose, where only the frequency should be locked. However, frequency control with the CPC resulted in the phase being locked. Thus, phase-lock operation was also achieved. The theoretical analysis of the phase-lock mechanism was confirmed through system simulations. We discussed about dead-zone problem caused by a time delay of circuits. We evaluated phase-shift direction detector to solve the dead zone problem. We designed the element blocks of the new PLL using a 0.25-μm CMOS process. We confirmed phase-lock operation through SPICE simulations of the MOSFET level. Moreover, we manufactured a trial circuit for the new PLL. We also confirmed phase-lock operation in the proposed PLL through measurements.
Journal
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- IEEJ Transactions on Electronics, Information and Systems
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IEEJ Transactions on Electronics, Information and Systems 131 (3), 490-498, 2011
The Institute of Electrical Engineers of Japan
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Details 詳細情報について
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- CRID
- 1390282679586131328
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- NII Article ID
- 10027804202
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- NII Book ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL BIB ID
- 10986027
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed