High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits/3 Bits

Hinosugi Mitsuki, Tsunekawa Yoshitaka, Miura Mamoru

doi:10.1541/ieejeiss1987.121.4_733

Bibliographic Information

Other Title

1桁2ビット/3ビット混合表現を用いた高速冗長2進加減算器
1ケタ 2ビット 3ビットコンゴウヒョウゲンオモチイタコウソクジョウチョウ 2シンカゲンザンキ

Search this article

Description

In this paper, we propose the very high-speed redundant binary adder-subtractor without sign changer. Firstly, we consider the subtraction method using redundant binary representation. So we propose the com-putation rule in subtraction. We design the redundant binary subtractor based on that computation rule. Using a hybrid representation method, which attempts to represent each digit by hybrid 2 bits/3 bits, we improve the subtractor at the same delay time as our already proposed high-speed redundant binary adder. Moreover, we develop the adder-subtractor without sign changer. The proposed adder-subtractor is logi-cally compared with the conventional adder-subtractor in terms of gate counts and delay time. Finally, by using PARTHENON, a CAD (Computer Aided Design) system for VLSI, this adder-subtractor is designed and evaluated, based on 5 volt, 0.6μm CMOS process technology. As a result, the speed of the proposed adder-subtractor is about 1.6 times as compared with the conventional adder-subtractor.

Journal

IEEJ Transactions on Electronics, Information and Systems

IEEJ Transactions on Electronics, Information and Systems 121 (4), 733-741, 2001

The Institute of Electrical Engineers of Japan

Keywords

Details 詳細情報について

Export