Hardware Acceleration of Bilateral Filters

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  • Isa Shuhei
    Department of Medical System Engineering, Faculty of Engineering,Chiba University
  • Yamada Chikatoshi
    Department of Information and Communication System Engineering,Okinawa National College of Technology
  • Nagata Yasunori
    Department of Electrical and Electronics Engineering,University of the Ryukyus

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  • Bilateral Filterのハードウェア化による高速化
  • Bilateral Filter ノ ハードウェアカ ニ ヨル コウソクカ

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A bilateral filter (BF) is a nonlinear filter that performs edge-preserving smoothing. In recent years, BF has been used in a wide variety of fields such as computer vision and computer graphics, and its applications include medical image processing. However, as compared to other filters, BF has large computational and time requirements. BF can be effectively used as a pre-processing step to speed up processing. In this paper, we consider a BF implemented at a one-chip circuit scale on a field-programmable gate array (FPGA). Furthermore, we aim to speed up floating-point pipelined arithmetic operations and processing by adopting a multiplication-based divider. The results show that hardware processing is approximately 20.93 times faster than software processing. Therefore, high-speed applications using BF are possible without the need for large equipment such as workstations or GPUs. Finally, it is suggested that real-time processing is feasible if a BF is applied as a pre-processing step.

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