Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic
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- Cho Seung-Il
- Graduate School of Science and Engineering, Yamagata University
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- Kim Seong-Kweon
- Department of Electronic and IT Media Engineering, Seoul National University of Science and Technology
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- Harada Tomochika
- Graduate School of Science and Engineering, Yamagata University
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- Yokoyama Michio
- Graduate School of Science and Engineering, Yamagata University
説明
To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197μW and 58.1μW at 3kHz and 10MHz, respectively.
収録刊行物
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- IEICE Electronics Express
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IEICE Electronics Express 10 (20), 20130716-20130716, 2013
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390282680188772480
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- NII論文ID
- 130003383469
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- ISSN
- 13492543
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可