Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic

DOI Web Site 2 Citations 6 References
  • Cho Seung-Il
    Graduate School of Science and Engineering, Yamagata University
  • Kim Seong-Kweon
    Department of Electronic and IT Media Engineering, Seoul National University of Science and Technology
  • Harada Tomochika
    Graduate School of Science and Engineering, Yamagata University
  • Yokoyama Michio
    Graduate School of Science and Engineering, Yamagata University

Description

To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197μW and 58.1μW at 3kHz and 10MHz, respectively.

Journal

  • IEICE Electronics Express

    IEICE Electronics Express 10 (20), 20130716-20130716, 2013

    The Institute of Electronics, Information and Communication Engineers

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