Loop acceleration by cluster-based CGRA

DOI Web Site 参考文献2件
  • Zhou Li
    Computer School, National University of Defense Technology
  • Liu Hengzhu
    Computer School, National University of Defense Technology
  • Zhang Jianfeng
    Computer School, National University of Defense Technology

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説明

This paper presents a cluster-based coarse grained reconfigurable array (CGRA) architecture and a corresponding modulo scheduling method for the inner-most loop. The reconfigurable clusters in this CGRA are composed of generic processing elements (PE) and shared PEs. The local connectivity of a cluster is utilized in the proposed mapping heuristic. Routing in the PE array is avoided because data transmission is within a cluster or between adjacent clusters in the heuristic. Experiment shows that the architecture and method outperform other modulo scheduling algorithms on CGRA. Better execution delay and resource utilization ratio can be achieved at 9.8%.

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 10 (16), 20130506-20130506, 2013

    一般社団法人 電子情報通信学会

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