An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating

DOI

説明

This paper proposes a method using partial reconfiguration to realize a compact regular expression matching engine, which can update a pattern quickly. In the proposed method, a set of partial circuits, each of which handles a different class of regular expressions, are provided in advance. When a regular expression pattern is given, a compact matching engine dedicated to the pattern is implemented on FPGA by combining the partial circuits according to the given pattern using partial reconfiguration. The method can update a pattern quickly, since it does not need re-design of a circuit. Experimental results show that the proposed method reduces 60% circuit size compared with the previous method without increasing the pattern updating time significantly.

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詳細情報 詳細情報について

  • CRID
    1390282680242408192
  • NII論文ID
    130004705281
  • DOI
    10.11185/imt.9.466
  • ISSN
    18810896
  • 本文言語コード
    en
  • データソース種別
    • JaLC
    • CiNii Articles
  • 抄録ライセンスフラグ
    使用不可

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