The Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing NCP Resin, Achieving the High Quality and Reliability
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- Shimote Yoshikazu
- Renesas Semiconductor Package & Test Solutions Co., Ltd.
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- Iwasaki Toshihiro
- J-Device Semiconductor Co., Ltd.
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- Watanabe Masaki
- J-Device Semiconductor Co., Ltd.
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- Baba Shinji
- Renesas Electronics Co., Ltd.
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- Kimura Michitaka
- Renesas Electronics Co., Ltd.
説明
The flip-chip ball-grid array (FCBGA) package has been applied in the fields of high-end server and network systems to achieve high performance in data processing. The demand for high-speed data processing in the global IT network and cloud markets has also continued its rapid expansion in recent years, so there is a strong need for the further development of FCBGA packages with high performance in response. We have developed a flip-chip technology with Cu-pillar bumps at a very fine staggered pitch of 30 μm, utilizing non-conductive paste (NCP) resin to adapt the package for use with devices having large numbers of pins, at least some of which carry high-speed signals. The keys to this flip chip technology are optimizing the conditions for the reaction of the NCP resin under the die and the effect of melting the solder when making connections. The effectiveness of different heights for the solder joints was studied to confirm the reliability of the package, and the results and a description of the technology are reported in this paper.
収録刊行物
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- Transactions of The Japan Institute of Electronics Packaging
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Transactions of The Japan Institute of Electronics Packaging 7 (1), 87-93, 2014
一般社団法人エレクトロニクス実装学会
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キーワード
詳細情報 詳細情報について
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- CRID
- 1390282680291007744
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- NII論文ID
- 130005130543
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- ISSN
- 18848028
- 18833365
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可