Analysis of Gate Disturbance Degradation by Nitridation of Flash Tunnel Oxide.

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  • Arai Masatoshi
    ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corporation, 19 Nishikujo-Kasugacho, Minami-ku, Kyoto 601-8413, Japan
  • Hashidzume Takahiko
    ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corporation, 19 Nishikujo-Kasugacho, Minami-ku, Kyoto 601-8413, Japan
  • Nitta Toshinari
    ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corporation, 19 Nishikujo-Kasugacho, Minami-ku, Kyoto 601-8413, Japan
  • Odake Yoshinori
    ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corporation, 19 Nishikujo-Kasugacho, Minami-ku, Kyoto 601-8413, Japan
  • Matsuo Ichiro
    ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corporation, 19 Nishikujo-Kasugacho, Minami-ku, Kyoto 601-8413, Japan

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In this work, an experimental analysis of gate disturbance degradation with negative bias stress caused by nitridation of flash tunnel oxide has been performed. Nitrided tunnel oxide successfully suppresses gate disturbance with positive bias stress, however, it enhances gate disturbance with negative bias stress. A similar gate polarity dependence has been observed in charge-to-breakdown and gate voltage shifts during Fowler-Nordheim stress. We propose the following dual-quality-layer model, which can explain all the polarity results. A poor-quality layer compared with base oxide is concurrently formed at the region where nitrogen atoms do not exist during nitridation. Subsequent to program/erase stress, more hole traps are created at the surface of tunnel oxide and modulate the energy band at the surface of tunnel oxide. Therefore, electrons can easily tunnel through the oxide with a negative bias stress because of the reduced barrier height at the surface of tunnel oxide.

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