Gate Length Dependence of Hot Carrier Reliability in Low-Temperature Polycrystalline-Silicon P-Channel Thin Film Transistors.

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  • Uraoka Yukiharu
    Graduate School of Materials Science, Nara Institute of Science and Technology, Takayama, 8916-5, Ikoma, Nara 630-0101, Japan
  • Morita Yukihiro
    Devices Development Center, Matsushita Electric Industrial Co., Ltd., 3-1-1 Yagumo-Nakamachi, Moriguchi, Osaka 570-8501, Japan
  • Yano Hiroshi
    Graduate School of Materials Science, Nara Institute of Science and Technology, Takayama, 8916-5, Ikoma, Nara 630-0101, Japan
  • Hatayama Tomoaki
    Graduate School of Materials Science, Nara Institute of Science and Technology, Takayama, 8916-5, Ikoma, Nara 630-0101, Japan
  • Fuyuki Takashi
    Graduate School of Materials Science, Nara Institute of Science and Technology, Takayama, 8916-5, Ikoma, Nara 630-0101, Japan

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Degradation of p-channel thin film transistor (TFT) under dc stress was investigated. We found that ON current and field-effect mobility increased. In order to clarify the cause of the degradation, we measured the degradation for various gate and drain voltage stress conditions. We found that the drain avalanche hot carrier effect was dominant. Analysis using an emission microscope also suggested that hot carriers had a strong relation with the degradation. Gate length dependence was analyzed with a device simulator based on the model considering the electron traps in the oxide. Areas where hot electrons are generated are independent of the gate length, therefore, TFTs with smaller gate length undergo more damage. Comparison between the simulation and the experimental values suggested that this model is valid.

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