A Partial-Ground-Plane(PGP) Silicon-on-Insulator(SOI) Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET) for Deep Sub-0.1-μm Channel Regime

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  • Yanagi Shin-ichiro
    High-Technology Research Center and Faculty of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan
  • Nakakubo Atsushi
    High-Technology Research Center and Faculty of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan
  • Omura Yasuhisa
    High-Technology Research Center and Faculty of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

書誌事項

タイトル別名
  • A Partial-Ground-Plane(PGP) Silicon-on-Insulator(SOI) Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET) for Deep Sub-0.1-.MU.m Channel Regime.
  • Partial Ground Plane PGP Silicon on Insulator SOI Metal Oxide Semiconductor Field Effect Transistor MOSFET for Deep Sub 0 1 マイクロ m Channel Regime

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説明

Silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) offers a number of advantages over conventional bulk silicon transistors. In this paper, we present a new SOI device structure called a “partial-ground-plane” SOI MOSFET down to 50 nm channel length. This new device shows good suppression of short-channel effect together with a small subthreshold swing and has a good driveability with a low leakage current.

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