Suppression of Gate Depletion in p+-Polysilicon-Gated Sub-40nm pMOSFETs by Laser Thermal Processing
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- Yamamoto Tomonari
- Device Development Department, Advanced LSI Development Division, FUJITSU Ltd., Akiruno Technology Center
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- Kubo Tomohiro
- Process Development Department, Advanced LSI Development Division, FUJITSU Ltd., Akiruno Technology Center
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- Okabe Ken-ichi
- Process Development Department, Advanced LSI Development Division, FUJITSU Ltd., Akiruno Technology Center
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- Sukegawa Takae
- Process Development Department, Advanced LSI Development Division, FUJITSU Ltd., Akiruno Technology Center
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- Wang Yun
- Ultratech Inc.
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- Lin Tengshing
- Ultratech Inc.
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- Talwar Somit
- Ultratech Inc.
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- Kase Masataka
- Process Development Department, Advanced LSI Development Division, FUJITSU Ltd., Akiruno Technology Center
Bibliographic Information
- Other Title
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- Suppression of Gate Depletion in p〔+〕-Polysilicon-Gated Sub-40nm pMOSFETs by Laser Thermal Processing
- Suppression of Gate Depletion in p<sup>+</sup>-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing
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Description
Laser thermal processing (LTP) was investigated as a gate pre-annealing technique and its advantages over rapid thermal annealing (RTA) with regard to both gate activation and suppression of boron penetration were confirmed by evaluating the electrical characteristics of sub-40 nm p-metal oxide semiconductor field effect transistors (pMOSFETs). Laser annealing transformed amorphous Si in which high doses of boron were implanted into poly-Si with highly activated boron profiles down to the gate/gate oxide interface. By suppressing gate depletion with suppressing boron penetration, LTP results in an on-current at Ioff=70 [nA/μm] that is 4% greater than that in a device fabricated using conventional RTA. The off-state Ig current that flows mainly from the p+ poly-Si gate to the drain overlap region is smaller in devices fabricated using LTP because the reduced roughness of the poly-Si gate/gate oxide interface in these devices reduces the local electric field enhancement.
Journal
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- Japanese Journal of Applied Physics
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Japanese Journal of Applied Physics 44 (4B), 2240-2244, 2005
The Japan Society of Applied Physics
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Details 詳細情報について
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- CRID
- 1390282681241347968
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- NII Article ID
- 10015703826
- 130004533692
- 210000057693
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- NII Book ID
- AA10457675
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- ISSN
- 13474065
- 00214922
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- NDL BIB ID
- 7306228
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- Text Lang
- en
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- Data Source
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- JaLC
- NDL Search
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed