Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop

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  • KIM SinNyoung
    Department of Communications and Computer Engineering, Kyoto University
  • TSUCHIYA Akira
    Department of Communications and Computer Engineering, Kyoto University
  • ONODERA Hidetoshi
    Department of Communications and Computer Engineering, Kyoto University JST, CREST

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This paper presents an analysis of radiation-induced clock-perturbation in phase-locked loop (PLL). Due to a trade-off between cost, performance, and reliability, radiation hardened PLL design need robust strategy. Thus, evaluation of radiation vulnerability is important to choose the robust strategy. The conventional evaluation-method is however based on brute-force analysis — SPICE simulation and experiment. The presented analysis result eliminates the brute-force analysis in evaluation of the radiation vulnerability. A set of equations enables to predict the radiation-induced clock-perturbation at the every sub-circuits. From a demonstration, the most vulnerable nodes have been found, which are validated using a PLL fabricated with 0.18µm CMOS process.

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