An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead

DOI Web Site 17 References Open Access
  • YOSHIDA Shinnosuke
    Dept. of Computer Science and Communications Engineering, Waseda University
  • SHI Youhua
    Waseda Institute for Advanced Study, Waseda University
  • YANAGISAWA Masao
    Dept. of Computer Science and Communications Engineering, Waseda University
  • TOGAWA Nozomu
    Dept. of Computer Science and Communications Engineering, Waseda University

Description

As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring the middle points, or check points of several speed-paths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

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