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Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes
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- UCHIKAWA Hironori
- Corporate R&D Center, Toshiba Corp.
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- HARADA Kohsuke
- Corporate R&D Center, Toshiba Corp.
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Description
We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.
Journal
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A (10), 2411-2417, 2009
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1390282681288888192
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- NII Article ID
- 10026859956
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- NII Book ID
- AA10826239
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- ISSN
- 17451337
- 09168508
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
- OpenAIRE
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- Abstract License Flag
- Disallowed
