Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis
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- WANG Nan
- Waseda University
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- CHEN Song
- University of Science and Technology of China
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- ZHONG Wei
- Waseda University
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- LIU Nan
- Waseda University
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- YOSHIMURA Takeshi
- Waseda University
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説明
Scheduling is a key problem in high level synthesis, as the scheduling results affect most of the important design metrics. In this paper, we propose a novel scheduling method to simultaneously optimize the leakage power of functional units with dual-Vth techniques and the number of registers under given timing and resource constraints. The mobility overlaps between operations are removed to eliminate data dependencies, and a simulated-annealing-based method is introduced to explore the mobility overlap removal solution space. Given the overlap-free mobilities, the resource usage and register usage in each control step can be accurately estimated. Meanwhile, operations are scheduled so as to optimize the leakage power of functional units with minimal number of registers. Then, a set of operations is iteratively selected, reassigned as low-Vth, and rescheduled until the resource constraints are all satisfied. Experimental results show the efficiency of the proposed algorithm.
収録刊行物
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E97.A (8), 1709-1719, 2014
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詳細情報 詳細情報について
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- CRID
- 1390282681288926464
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- NII論文ID
- 130004679254
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- ISSN
- 17451337
- 09168508
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- 本文言語コード
- en
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- 資料種別
- journal article
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- OpenAIRE
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