Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits

DOI Web Site 1 Citations 23 References
  • Molinar Jesus E.
    Departamento de Electronica y Sistemas Computacionales, Tecnologico Nacional de Mexico, ITCG
  • Gurrola Marco A.
    Departamento de Electronica, CUCEI, Universidad de Guadalajara
  • Padilla Ivan R.
    Departamento de Electronica, CUCEI, Universidad de Guadalajara
  • Ocampo Juan J.
    Departamento de Electronica, Universidad Autonoma Metropolitana
  • Bonilla Carlos A.
    Departamento de Electronica, CUCEI, Universidad de Guadalajara
  • Amezcua Jose M.
    Departamento de Electronica y Sistemas Computacionales, Tecnologico Nacional de Mexico, ITCG

Search this article

Description

<p>This letter details a novel floating-bulk transistor technique for low-voltage design. The approach is derived from two previous well-known techniques: bulk-driven and quasi floating-gate. The floating-bulk technique uses an input capacitive coupling through a floating bulk of a PMOS allowing modulation of the drain current. A fabricated common-source amplifier was tested on CMOS 0.5 µm technology and the feasibility of the proposal was demonstrated.</p>

Journal

  • IEICE Electronics Express

    IEICE Electronics Express 17 (3), 20190748-20190748, 2020

    The Institute of Electronics, Information and Communication Engineers

Citations (1)*help

See more

References(23)*help

See more

Keywords

Details 詳細情報について

Report a problem

Back to top