A Hardware-Oriented Echo State Network for FPGA Implementation

DOI オープンアクセス
  • Honda Kentaro
    Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology
  • Tamukoh Hakaru
    Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology

説明

This paper proposes implementation of an echo state network (ESN) to field programmable gate array FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200[MHz] of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit.

収録刊行物

キーワード

詳細情報 詳細情報について

  • CRID
    1390283659853192576
  • DOI
    10.5954/icarob.2020.os20-1
  • ISSN
    21887829
  • 本文言語コード
    en
  • データソース種別
    • JaLC
    • Crossref
    • OpenAIRE
  • 抄録ライセンスフラグ
    使用不可

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