SPT: A Development Tool for Block Ciphers with Accelerators
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- IWAI Keisuke
- National Defense Academy of Japan
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- WATANABE Masashi
- Japan Maritime Self Defence Force
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- TANAKA Hidema
- National Defense Academy of Japan
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- KUROKAWA Takakazu
- National Defense Academy of Japan
Bibliographic Information
- Other Title
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- アクセラレータ用暗号開発ツールSPT
Abstract
Cryptographic processing to protect personal data, sensitive data, and so on, is executed on every devices. On the other hand, computer accelerators, such as GPU, are widely used from embed systems to high-end supercomputers. However, they urge programmers to optimize programs for each devices to exploit accelerator's performance. It is too difficult to optimize a program for each accelerator, because architectures of accelerators are various today. Therefore, cryptographic processing using accelerator will achieve high-speed and low-power processing. In this paper, a program development tool for accelerators specialized for block ciphers named “Schematic to Program Translator (SPT)” is proposed. SPT generates programs for accelerators including GPGPU and FPGA from a schematic of cipher algorithms. Evaluation results show that performance of generated programs by SPT achieves identical performace for CPU and FPGA, and achieves half the perfomance for GPU compared with hand generated programs.
Journal
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- 電子情報通信学会論文誌D 情報・システム
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電子情報通信学会論文誌D 情報・システム J100-D (6), 627-638, 2017-06-01
The Institute of Electronics, Information and Communication Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1390283687150558080
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- ISSN
- 18810225
- 18804535
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- Text Lang
- ja
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- Data Source
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- JaLC
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- Abstract License Flag
- Disallowed