Japanese High-level Synthesis Tools for FPGA Hardware Acceleration
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- WATANABE Minoru
- Shizuoka University
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- SANO Kentaro
- Tohoku University
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- TAKAMAEDA Shinya
- Hokkaido University
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- MIYOSHI Takefumi
- WasaLabo, LLC.,e-trees.Japan
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- NAKAJO Hironori
- Tokyo University of Agriculture and Technology
Bibliographic Information
- Other Title
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- FPGAハードウェア・アクセラレーション向け日の丸高位合成ツール
Abstract
Recently, field programmable gate arrays (FPGAs) are being widely used for consumer electronics, automotive embedded systems, space embedded systems, and so on. Since the performances of FPGAs were much lower than those of application specific integrated circuits (ASICs) until around 2006 due to their look-up table and switching matrix architectures, FPGAs were only used for prototyping systems, tests, research equipment, and so on and could not be used for high-performance systems. However, subsequently, FPGAs have been being fabricated by using the latest VLSI technology while ASICs could only use retro process technologies. Up to now, the performances of FPGAs have been improved drastically. A lot of papers have presented that hardware accelerators on FPGAs are useful for increasing the performances of a software operations on computer systems. Moreover, XILINX and Altera are currently providing general-purpose high-level synthesis tools. However, the performances are not better than those of designs using hardware description language. Therefore, this paper introduces some new Japanese high-level synthesis tools which are useful for specific domains.
Journal
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- 電子情報通信学会論文誌B 通信
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電子情報通信学会論文誌B 通信 J100-B (1), 1-10, 2017-01-01
電子情報通信学会
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Keywords
Details 詳細情報について
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- CRID
- 1390283687150899840
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- ISSN
- 18810209
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- Text Lang
- ja
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- Data Source
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- JaLC
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- Abstract License Flag
- Disallowed