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- CAO Jianli
- School of Software Technology, Dalian University of Technology
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- CHEN Zhikui
- School of Software Technology, Dalian University of Technology
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- WANG Yuxin
- School of Computer Science and Technology, Dalian University of Technology
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- GUO He
- School of Software Technology, Dalian University of Technology
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- WANG Pengcheng
- Jianghuai College of Ahui University
抄録
<p>Like many processors, GPGPU suffers from memory wall. The traditional solution for this issue is to use efficient schedulers to hide long memory access latency or use data prefetch mech-anism to reduce the latency caused by data transfer. In this paper, we study the instruction fetch stage of GPU's pipeline and analyze the relationship between the capacity of GPU kernel and instruction miss rate. We improve the next line prefetch mechanism to fit the SIMT model of GPU and determine the optimal parameters of prefetch mechanism on GPU through experiments. The experimental result shows that the prefetch mechanism can achieve 12.17% performance improvement on average. Compared with the solution of enlarging I-Cache, prefetch mechanism has the advantages of more beneficiaries and lower cost.</p>
収録刊行物
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E104.A (5), 773-785, 2021-05-01
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390287907271097472
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- NII論文ID
- 130008032764
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- ISSN
- 17451337
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可