Logic Design with Three-Level NAND Network

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  • NANDゲート3段による論理回路設計

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Two valued logic functions can be realized in a three level NAND network with fewer number of connecting lines or gates than a NOT AND OR network with single railed inputs. We exploited a new design system (on FACOM M380Q OS IV /MSP FORTRAN77 V1 OL30) using bit patterned threelevel NAND data structure with bidirectionally linked lists. This new system could generate an approximate solution eleven times faster than the three level NAND network design system formerly developed in our laboratory. We also investigated realizing logic networks using compound AND OR gates that have the same propagation delay time as that of two level logic circuits. We could demonstrate designing logic networks with the compound AND OR gates reduce the total number of gates and connecting lines and propagation delay time.

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