A fast-transient dual loop LDO with high PSR

DOI Web Site 参考文献28件
  • Fang Hang
    School of Microelectronics, Xidian University
  • Jin Gang
    School of Microelectronics, Xidian University
  • Liu Weifeng
    School of Microelectronics, Xidian University
  • Wu Hao
    School of Computer Science, Xi’an Shiyou University
  • Tang Hualian
    School of Microelectronics, Xidian University

抄録

<p>In this work, the design of a 0.18µm CMOS dual loop capacitor-less low-dropout regulator (LDO) to achieve fast-transient response and good power supple rejection (PSR) is proposed for system-on-chip (SoC) power supply. The proposed LDO has a high slew-rate fast loop for enhancing transient response capability, and the high gain slow loop to improve PSR. Results show that the LDO consumes 100µA quiescent current, delivering a 50mA load current over a 30pF load. The maximum transient output-voltage variation is within 10% of the output voltage with recovery time of less than 81ns with a load step between 500µA and 50mA with 50ns edge times. The PSR is better than 50dB at 1MHz.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 21 (9), 20240172-20240172, 2024-05-10

    一般社団法人 電子情報通信学会

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