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- NIWA Naoya
- Keio University
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- SHIKAMA Yoshiya
- Keio University
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- AMANO Hideharu
- Keio University
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- KOIBUCHI Michihiro
- National Institute of Informatics PRESTO JST
抄録
<p>Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.</p>
収録刊行物
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E106.D (2), 170-180, 2023-02-01
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390576435496450688
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- ISSN
- 17451361
- 09168532
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可