LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure
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- Sadasue Tamon
- Information and Communications Engineering, Tokyo Institute of Technology
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- Isshiki Tsuyoshi
- Information and Communications Engineering, Tokyo Institute of Technology
説明
<p>As the scale of digital circuit design increases, design and verification using conventional hardware description languages (HDLs), such as verilog-HDL and VHDL, limit efficiency. Consequently, high level synthesis (HLS), as well as domain specific languages (DSLs), which alternates conventional HDLs, are beginning to garner attention. We proposed a design framework that uses the C language as a register transfer level descriptive language. In this study, we introduced a LLVM compiler infrastructure to extend our previous work, support the C/C++ standard as the input code, and aggressively optimize the circuit design. In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. We demonstrated the conversion of the input of C/C++ code into the verilog code, optimize its logic, and construct pipelined logic to achieve the original behavior in multiple clock cycles. Our framework offers a significantly efficient system-level hardware design and a powerful debugging environment with software development platforms and tool-sets. The generated hardware logic performs as well as or better than hand-written logic using conventional HDLs.</p>
収録刊行物
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- IPSJ Transactions on System and LSI Design Methodology
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IPSJ Transactions on System and LSI Design Methodology 16 (0), 12-26, 2023
一般社団法人 情報処理学会
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詳細情報 詳細情報について
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- CRID
- 1390576535082672000
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- ISSN
- 18826687
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- OpenAIRE
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- 抄録ライセンスフラグ
- 使用不可
