A Design and Evaluation of 0.5V Filter-less Digital Phase Locked Loop With A New Clock Synchronization Algorithm

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  • 新たな同期アルゴリズムを用いた0.5V動作フィルタレスデジタルPLL回路の設計と評価
  • アラタ ナ ドウキ アルゴリズム オ モチイタ 0.5V ドウサ フィルタレスデジタル PLL カイロ ノ セッケイ ト ヒョウカ

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Abstract

<p>In this paper, we design and evaluate the 0.5V subthreshold filter-less digital PLL. Under the subthreshold region, it's very difficult for analog type PLL using LPF to operate at 0.5V power supply due to narrow signal voltage range. Thus, we design the filter-less digital PLL circuit using our proposed synchronization algorism. As a result, we succeed synchronization without LPF. Power consumption is 373nW at 1048kHz synchronous operation.</p>

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