Design and Synthesis of Ternary CMOS Logic Circuits and D-Element
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- Nagata Yasunori
- Faculty of Engineeering, University of the Ryukyus
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- Kawaguchi Mayuka F.
- Graduate School of Information Science and Technology,Hokkaido University
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- Yamada Chikatoshi
- Okinawa National College of Technology
Bibliographic Information
- Other Title
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- 3値CMOS論理回路とD-素子の構成
- 3チ CMOS ロンリ カイロ ト D-ソシ ノ コウセイ
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Description
<p>In this paper, a design technique for ternary logic function circuits based on CMOS design are proposed. The circuits operate as B-ternary (binaric ternary) logic functions that are useful in asynchronous systems or self-checking circuits of fault-tolerant systems. Further, a special logic circuit, D-element, is proposed. D-element is designed for asynchronous systems like Mullers C-element in binary circuits. The circuits' SPICE simulations are provided to show their efficacy.</p>
Journal
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- IEEJ Transactions on Industry Applications
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IEEJ Transactions on Industry Applications 139 (2), 143-148, 2019-02-01
The Institute of Electrical Engineers of Japan
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Details 詳細情報について
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- CRID
- 1390845713049064960
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- NII Article ID
- 130007600732
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- NII Book ID
- AN10012320
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- ISSN
- 13488163
- 09136339
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- NDL BIB ID
- 029496076
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL Search
- Crossref
- CiNii Articles
- OpenAIRE
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- Abstract License Flag
- Disallowed