Design of Main Circuit for an SiC-MOSFET Inverter Using a Thick Copper Multilayer PCB to Minimize Stray Inductance

DOI Web Site Web Site 2 Citations 4 References
  • Ishikawa Kohsuke
    Graduate School of Information Science and Technology, Hokkaido University
  • Ogasawara Satoshi
    Graduate School of Information Science and Technology, Hokkaido University
  • Takemoto Masatsugu
    Graduate School of Information Science and Technology, Hokkaido University
  • Orikawa Koji
    Graduate School of Information Science and Technology, Hokkaido University

Bibliographic Information

Other Title
  • 低インダクタンスを実現する厚銅多層基板を用いたSiC-MOSFETインバータの主回路設計
  • テイインダクタンス オ ジツゲン スル コウ ドウ タソウ キバン オ モチイタ SiC-MOSFET インバータ ノ シュ カイロ セッケイ

Search this article

Description

<p>Inverters using SiC or GaN power devices can achieve high frequency and high efficiency operation. To achieve high efficiency, the switching characteristics of these power devices are important because stray inductances in the main circuit of the inverter have a strong influence on the switching characteristics. To reduce switching loss and surge voltage, minimization of stray inductance in the main circuit is required for a high-frequency PWM inverter. This paper describes design guidelines for high-frequency inverters that achieve low inductance. The PCB design guideline on a thick multilayer PCB is derived from the inductance calculation using 3D-FEA. It is shown experimentally that the stray inductance of the designed PCB can be reduced to the same level as the inductance inside the power devices. Experimental results verify that a prototype can achieve high-speed switching and suppress a surge voltage. A load test is demonstrated to evaluate the main circuit efficiency in a half-bridge inverter at 100kHz.</p>

Journal

Citations (2)*help

See more

References(4)*help

See more

Keywords

Details 詳細情報について

Report a problem

Back to top