A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

DOI Web Site 被引用文献6件 参考文献30件
  • Chen Mingliang
    School of Aeronautics and Astronautics, Zhejiang University
  • Wu Keke
    School of Aeronautics and Astronautics, Zhejiang University
  • Shen Yupeng
    School of Aeronautics and Astronautics, Zhejiang University
  • Wang Zhiyu
    School of Aeronautics and Astronautics, Zhejiang University
  • Chen Hua
    School of Aeronautics and Astronautics, Zhejiang University
  • Liu Jiarui
    School of Aeronautics and Astronautics, Zhejiang University
  • Yu Faxin
    School of Aeronautics and Astronautics, Zhejiang University

説明

<p>This paper presents a 14bit 500MS/s SHA-less pipelined analog-to-digital converter (ADC) implemented in 40nm CMOS. A high-linearity pseudo-differential push-pull input buffer with an anti-oscillation technique and a nonlinear parasitism eliminate technique is proposed to stably drive the pipelined stages while keeping low distortion. Moreover, a digital controlled aperture-error calibration is also employed with offset of comparators compensated in advance. Measurement results show that the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 66.29dB and a spurious-free-dynamic-range (SFDR) of 85.62dBc at 80.1MHz input.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 18 (11), 20210171-20210171, 2021-06-10

    一般社団法人 電子情報通信学会

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