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- Nishizawa Shinichi
- Fukuoka University
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- Lin Shih-Ting
- National Yang Ming Chiao Tung University
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- Li Yih-Lang
- National Yang Ming Chiao Tung University
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- Onodera Hidetoshi
- Osaka Gakuin University
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説明
<p>This paper reports a supplemental process design kit (PDK) for ASAP7 PDK using Synopsys design flow. ASAP7 is a PDK for “predictable” 7-nm FinFET technology node. ASAP7 PDK is useful for academical and educational purpose, however it only supports Cadence platform for Place and Route. A supplemental PDK is designed for ASAP7 to use Synopsys platform for Place and Route. This PDK is opened at the author's GitHub site for both acamemical and educational usage.</p>
収録刊行物
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- IPSJ Transactions on System and LSI Design Methodology
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IPSJ Transactions on System and LSI Design Methodology 14 (0), 24-26, 2021
一般社団法人 情報処理学会
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詳細情報 詳細情報について
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- CRID
- 1390851883593854720
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- NII論文ID
- 130008071971
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- ISSN
- 18826687
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- OpenAIRE
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- 抄録ライセンスフラグ
- 使用不可